摘要
在高阶宽带电路交换专用集成电路(ASIC)芯片设计中,输入数据的帧定位和数据重排操作需要占用大量的逻辑电路。文章提出了一种流水线结构的帧定位电路设计方式,给出了STM-16码流的帧定位和数据重排的两种不同电路设计实现方案。试验结果表明,采用流水线结构设计实现的STM-16帧定位电路,可明显减小电路规模,降低芯片功耗,提高芯片的可靠性和整体性能。
Large amounts of logic circuits are required for the frame alignment and rearrangement of the input data in the design of ASIC chips for the high-order broadband （STM-16） circuit switching. A frame alignment circuit design by using the pipeline technology is presented and two different circuit design schemes for the above functions given. The test results show that by using this scheme the circuit size is obviously reduced, the chip power consumption decreased and its reliability and performances improved.
出处
《光通信研究》
北大核心
2008年第1期17-19,共3页
Study on Optical Communications
基金
国家"八六三"计划资助项目(2003AA1Z1190)
陕西省教育厅项目资助课题(07JC14)
