摘要
本文介绍了在FPGA上利用Verilog HDL语言实现语音记录仪的设计。系统以Altera公司的NiosII嵌入式软处理器为核心,采用硬盘作为数据储存媒介,自定义Verilog模块实现语音信号的A/D转换及控制硬盘读写。使用QuartusII平台自带的SOPC Builder设计工具,将处理软核,外围设备和用户定义逻辑集成到一片FPGA芯片上,海量的存储空间能实现对语音长时间的记录减小了系统体积,提高了处理速度,增强系统的实用性。实验结果表明:该系统具有电路接口简单,可靠性高,录音时间超长等特点,具有广阔的应用前景。
This paper introduces the design of an embedded audio recording system by VerilogHDL on FPGA. This system uses embedded soft processor NiosⅡ as kernel, storages large amounts of audio data in the hard drive, and makes use of custom logic module to implement A/D and hard drive control. The design method of integrating NiosⅡ soft processor, peripheral equipments and custom logic module all on a FPGA by using SOPC Builder, which satisfies the requirement of real-time audio data recording, improves the processing speed and strengthens the practicability of the system. The simulation result indicates the system has simple circuit interface, high reliability and very long recording time, it has a wide application prospect.
出处
《电子测量技术》
2008年第4期190-193,共4页
Electronic Measurement Technology
