摘要
针对现有HDB3(三阶高密度双极性)编码器中存在编码复杂、输出延时长等缺陷,提出了一种基于分组编码、统一极性判断和位置极性判断的HDB3编码器快速设计方法,并相应提出了基于极性判别的快速译码设计方法,避免了译码过程中的取代节检测.在QuartusⅡ5.1下的仿真结果表明,提出的编译码方法具有消耗资源少、工作速度快的优点,与现有方法相比,编码和译码占用的逻辑单元数分别减少25%和40%,扇出数分别减少29.4%和50.9%.经实际测试,编译码器功能正确,可用于实际电路中.
To solve the drawbacks of the existing HDB3 （high density bipolar 3 ） encoders, such as high encoding complexity and long output delay, a fast design method for HDB3 encoders based on block encoding, unified polarity judgment and position polarity judgment was proposed. As a result, a fast design method for decoding was proposed based on polarity judgment to avoid checking substitute nodes in the process of decoding. Simulation results in Quartus Ⅱ 5.1 show that the proposed encoding and decoding methods have advantages over the existing methods in resource consumption and operation speed. Compared with the existing methods, with the proposed encoding and decoding methods the number of logic elements is dropped by 25% for encoding and 40% for decoding, and the fan-out numbers for encoding and decoding are decreased by 29.4% and 50, 9% respectively. The test result indicates that the new encoder and decoder have a right function and can be applied to actual circuits.
出处
《西南交通大学学报》
EI
CSCD
北大核心
2008年第1期25-28,76,共5页
Journal of Southwest Jiaotong University
基金
宁波市工业科研攻关资助项目(2005B100003)
宁波市青年基金资助项目(2005A620001)
关键词
HDB3码
VHDL
编译码器
极性判别
HDB3 （ high density bipolar 3 ） code
VHDL hardware description language ）
encoder and decoder
polarity （very high speed integrated circuits judgment
