摘要
提出一种钟控伪随机序列发生器的加速机制,可以使序列发生器在一个时钟周期内得到前进n步的结果,在硬件实现时使得序列发生器的工作频率提高n倍。此加速机制可应用于钟控序列发生器和序列密码发生器的密钥预置。
This paper presents an acceleration mechanism used for clock-controlled pseudo random sequence generator, with which the state of sequence generator in next n steps can be got within a single clock cycle, therefore the maximum working frequency of the sequence generator can rise to n times of the regular circuit. The acceleration mechanism can be used in acceleration of clockcontrolled sequence generator and key preset of stream cipher generator.
出处
《航天器工程》
2008年第2期44-47,共4页
Spacecraft Engineering
基金
国家“863”计划项目(2004AA741071)
关键词
序列密码
钟控序列发生器
加速机制
stream eipher
clock-controlled sequence generator
acceleration mechanism
