摘要
提出一种可实现占空比为50%的7倍时钟分频电路的高可靠性设计方案,并分别给出由分立元件组构和由Verilog HDL语言描述的2种实现方法。与已有方案相比,该设计不仅可以节省器件资源,而且完全避免了冒险现象对于分频时钟波形造成的影响。在Quartus环境下,分别对门级设计和基于Verilog HDL语言的行为级描述进行仿真验证,结果显示该方案合理可行。
Design method of high - reliability 1 ： 7 clock frequency divider with half duty cycle is brought forward, and then implementation method based on separate component or described by Verilog HDL is presented. Comparing with former design method,not only can the method economize on hardware resource, but it can be absolutely avoided that waveform of divided frequency clock is interfered by hazard in this method. After function of gate level design as well as behavior level design based on Verilog HDL is simulated in Quartus software,the method is proved logical and feasible as a result.
出处
《现代电子技术》
2008年第6期12-13,18,共3页
Modern Electronics Technique
