摘要
设计和实现了一个应用于音频∑-Δ模数转换器的数字抽取滤波器.该抽取滤波器采用多级多采样率结构,由梳状滤波器、补偿滤波器和2个FIR半带滤波器构成.补偿滤波器补偿梳状滤波器的通带滚降,补偿后整个抽取滤波器带内纹波小于0.006 dB,同时补偿滤波器实现了2倍降采样,减少了一个FIR半带滤波器的硬件开销.滤波器系数均采用规范符号编码实现,避免使用规模很大的乘法器单元.数字抽取滤波器采用SMIC 0.18μm CMOS工艺实现,芯片测试表明,该滤波器对256倍过采样率、三阶∑-Δ调制器的输出码流进行处理得到的信噪比达到107 dB,能够满足高端音频模数转换器的要求.
A multistage decimation filter for audio oversampling∑-Δ A/D converter was designed and implemented in SMIC 0.18 pan CMOS process. The filter consists of a cascaded-integrator-comb （CIC） filter, a compensation filter and two FIR half-band filters. The compensation filter offsets the droop of the CIC filter, the pass-band ripple of the decimation filter was less than 0.006 dB after compensation. A twice decimation was also achieved by the compensation filter, which resulted in hardware saving of a half-band filter. Canonic signed digit （CSD） number system with shifters and adders was used instead of large multipliers. By processing the bit stream from a 3-level ∑-Δ modulator with an oversampling ratio of 256, a signal-to-noise ratio of 107 dB was obtained for the filter, which was sufficient for the high-end audio applications.
出处
《天津大学学报》
EI
CAS
CSCD
北大核心
2007年第12期1421-1425,共5页
Journal of Tianjin University(Science and Technology)
关键词
数字抽取滤波器
过采样模数转换器
补偿滤波器
规范符号编码
decimation filter
oversampling analog-to-digital converter
compensation filter
canonic signed digit
