摘要
介绍了相位调频式DPSK通讯原理,并利用VHDL语言设计了相位调频式DPSK基带数据收发器芯片。同时给出了该芯片的组成框图,利用QUARTUSII4.2开发软件对核心模块进行了仿真。将设计信息下载于ALTERA公司的cycloneEP1C6T144C8 FPGA芯片中,进行了样机的实际测试。该芯片采用了现代的EDA技术,自顶向下的设计理念,具有FPGA/CPLD芯片的低功耗、抗干扰、宽带宽的特性,具有在系统编程的特点,因此在产品的研发、维护和后期升级上面,优于其它的专用ASIC通讯芯片。
The principle of phase- frequency modulation DPSK communication is introduced and base -band data receiver/transmitter chip is devel- oped by means of VHDL in this paper. We simulate the core module with quartusII4.0 software, download the design information into EPF10K10 chip, and test the prototype. The chip is designed for low power dissipation, high noise immunity and wide bandwidth, using modern EDA technology and up - to - down design concept. It is better than the other special - purpose ASIC communication chips in the development of product,maintainance and later upgrade, since the chip is characterized by its onsystem programmability.
出处
《机械与电子》
2008年第1期69-71,共3页
Machinery & Electronics
