摘要
可变字长编解码是H.264标准中的一项重要技术,本文设计了一种基于H.264标准的高速可变字长解码器。设计上采用自顶向下的设计方法,首先进行系统结构设计,根据码流特点进行硬件结构划分,尽可能多地进行并行解码,采用桶形移位器。并用C语言设计了系统模型,由C模型为RTL的仿真提供测试向量,在设计的各个阶段都进行了仿真,以保证每个阶段设计的正确性。该模块已通过FPGA验证,并用0.18μm的SMIC工艺库进行DC综合,电路规模约1.4万门左右,最高频率可以达到200MHz,可对H.264高清码流进行实时解码。
Variable length decoding is a very important technology of H. 264. This paper proposes an implementation of high speed variable length decoder for H. 264. A Top-Down method is used. The first part of system structure design, then the hardware structure division as more as possible for parallel decoding is operated in term of the code flow. The barrel-shifter which is based on parallel structure is used, and the C code is used to generate the test vectors for verifying the RTL simulation. The whole design has been verified by FPGA. After DC synthesizing with 0. 18μm SMIC18 library,the size of circuits reached 14k gates, and the highest frequency reached 200 MHz. The design can decode the High-Definition video in real-time for H. 264.
出处
《电子测量技术》
2007年第10期7-10,32,共5页
Electronic Measurement Technology
基金
宁波市高新技术研发与产业化计划项目资助
