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采用相邻耦合动态功耗优化的低功耗布线方法 被引量:3

Low power routing method based on reducing adjacent signal coupling dissipation
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摘要 根据相邻信号线的逻辑电位计算两线耦合动态功耗.将这种方法应用于计算N位总线的M个连续时刻的功耗,得到N位总线的平均功率因子,以反映N位总线的相邻耦合平均动态功率.根据程序地址总线的数据,搜索得到对应最小平均功率因子的总线内信号线的排布方式,实现最优的低功耗总线布线,使程序地址总线的动态功耗降低了38.2%. According to the logic value of an adjacent signal, the coupling dynamic dissipation of the adjacent signal is computed. The method is used in calculating the dynamic dissipation of the N bit bus during M, so the average dissipation factor pM is obtained to reflect the average power of the N bit bus. With the datafile of the program address bus, the best routing of the bus is searched for by computing the lowest PM. As a result, the dynamic dissipation of the bus is reduced by 38.2%.
出处 《西安电子科技大学学报》 EI CAS CSCD 北大核心 2007年第5期712-715,共4页 Journal of Xidian University
基金 国家自然科学基金资助(60606006) 国家自然科学基金资助(60676009)
关键词 低功耗 相邻信号 功耗因子 布线 low-power adjacent signal dissipation factor routing
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  • 1Sunpack H, KiSC, Taewhan K. Bus-invert Coding for Low-power I/O-a Decomposition Approach[C]//MWSCAS- 2000: V2. Lansing: IEEE Circuits and Systems Society, 2000: 750-753. 被引量:1
  • 2Stan M R, Burleson W P. Bus-invert Coding for Low-power I/O”[J]. IEEE Trans on VLSI Syst, 1995, 3(3) : 49-58. 被引量:1
  • 3Benini L, DeMicheli G, Macii E, et al. Asymptotic Zero-transition Activity Encoding for Address Busses in Low-power Microprocessor-based Systems[C]// Proc 7th Great Lakes Symp VLSI. Urbana-Champaign: IEEE, 1997: 77-82. 被引量:1
  • 4Ranganathan N, Henriques S. High-speed VLSI Designs for Lempel-ziv-based Data Compression[J]. IEEE Trans on Circuit Syst Ⅱ, 1993, 40(2): 96-106. 被引量:1
  • 5Ikeda K M, Asada K. Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-book Method[C]// Ninth Great Lakes Symposium. Los Alamitos: IEEE Computer Society, 1999: 368-371. 被引量:1
  • 6Chandrakasan A P, Brodersen R W. Low Power Digital CMOS Design[M]. New York: Kluwer Academic, 1995. 被引量:1
  • 7Sotiriadis P P, Chandrakasan A. Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep Sub-micron Technologies[C]//Proc IEEE/ACM Int Conf Computer-Aided Design. Los Alamitos: IEEE Computer Society, 2000: 322-327. 被引量:1
  • 8Sotiriadis P P. Interconnect Modeling and Optimization in Deep Sub-micron Technologies [D]. Massachusetts: Massachusetts Institute of Technology, 2002. 被引量:1

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