摘要
绝大部分ASIC设计工程师在实际工作中都会遇到多时钟域设计的问题,多时钟域设计的一个难题是如何避免亚稳态的产生。异步FIFO是一种不同时钟域之间传递数据的常用方法。避免亚稳态问题及空满控制信号的产生是异步FIFO设计的两个关键。本文针对异步时序产生的问题提出了一种新的异步FIFO设计方案。用这样一个异步FIFO模块实现FPGA内部不同时钟系统之间的数据接口,它们之间不需要互相握手,只需跟接口FIFO模块进行交互就可以了,使设计变得非常简单和容易。此异步FIFO基于Altera公司的Cyclone系列实现的,采用VHDL语言设计,通过对设计进行简单的修改,即可用于各种不同的系统的设计,经过充分测试和优化,该异步FIFO运行稳定,占用FPGA内部资源也非常少。
Most of the ASIC＇s ever designed are driven by multiple asynchronous clocks. An important problem in multi-clock domain design is how to avoid metastability. Asynchronous FIFO is a general way to communicate between different clock domains. Metastability and how to generate empty and full flag correctly is key in the design of asynchronous FIFO. Aiming at the issue of asynchronous design, this paper proposes a new method to overcome these problems. It uses the asynchronous FIFO to interface between clock systems inside FPGA, and there is no need to shake hand with the other clock system. In this method the interface becomes very easy and also stable, and the two sides operate inside its own clock system. The asynchronous FIFO is based on the Cyclone serial FPGA device. It is designed with VHDL, and can be applied to many system designs with simple modification. It is tested carefully and occuoies small resource.
出处
《微计算机信息》
北大核心
2007年第01Z期246-248,共3页
Control & Automation
基金
广东省自然科学基金(04009469)
