摘要
本文以Altera公司的FPGA为硬件平台,以MAX-PLUSII为设计工具,实现直接序列扩频(DSSS)发射机,顶层采用图形设计方式,各模块是基于Verilog HDL设计的。本设计中待发射信息是以循环读ROM的方式读取,信道编码采用(2,1,7)卷积码,扩频模块采用扩频长度255的kasami码,极性变换模块为3bit量化模式,内插模块为每两比特间插入7bit,输出滤波为16阶的FIR滤波器。文中给出了本设计实现的系统整体方框图,Verilog HDL代码实现及其仿真结果。仿真结果表明本设计精确度高,稳定且输出无毛刺。
This paper presented an implementation of a direct sequence spread spectrum transmitter, which used FPGA as a hardware platform, and Max- plusⅡ as a design tool. And the modules were designed using Verilog HDL and the top layer was designed based on Graphic method. In this design, Bits to be transmitted are read from ROM circularly, and the channel coding utilizes （2,1,7） convolution codes. The spread spectrum module adopted kasami codes with a spread length 255. And a 3 bit quantization is used for polar transformation. Between every bit, 7 bits were inserted in interpolation module. The output filter is a 16 level FIR filter. The Verilog HDL codes, block diagram of the whole system,and the simulation results were presented in this paper.The result of the simulation showed that this is a high acurate and stable design without any glitch.
出处
《微计算机信息》
北大核心
2007年第17期185-190,共6页
Control & Automation
基金
国家自然科学基金项目(60574088)
