期刊文献+

Banyan网输入输出排队的神经网络调度及其实现 被引量:3

Neural Network-Controlled Banyan Network with Input-Output-Queueing and Its Implementation
下载PDF
导出
摘要 Banyan网是一种多级互联网络,它广泛地应用在ATM交换结构中.Banyan网输入排队的神经网络调度方法已有文章提出,但其硬件实现比较复杂.本文提出了一种Banyan网输入输出排队的神经网络调度方法,它的硬件实现容易.计算机模拟结果表明,该调度方法是非常有效的.在此,还给出了该系统的硬件实现方法. The Banyan network is a kind of multistage interconnection networks (MINs) and is widly used as a building block in ATM switch fabric designs. The neural network controlled Banyan networks have been proposed in some papers but its hardward implementation is complicated. In this paper we propose a new neural network controlled Banyan network with input-output-queueing. Its neural network controller is easy to implement. Our simulation results show that this mathod is very efficient. Here,we give its hardware implementation.
作者 南华 刘泽民
机构地区 北京邮电大学
出处 《电子学报》 EI CAS CSCD 北大核心 1997年第7期120-123,共4页 Acta Electronica Sinica
关键词 ATM 神经网络 信元调度 BANYAN网 B-ISDN ATM,Queueing,Switching,Neural network, Scheduling.
  • 相关文献

同被引文献31

  • 1雷振明.宽总线ATM交换结构[J].通信学报,1994,15(3):109-114. 被引量:2
  • 2贺飞云,闻懋生.一种自选路由ATM容错交换网络[J].电子学报,1997,25(1):28-32. 被引量:2
  • 3[2]Hluchyj M G, Karol M J. Queueing in high -performance packet switching. IEEE JSAC, 1988; 6(9): 1587 ~ 1597 被引量:1
  • 4[3]Brown T X, Liu K H. Neural network design of a banyan network controller. IEEE JSAC, 1990; 8(8): 1428 ~ 1438 被引量:1
  • 5[5]Fantacci R, Forti M, Marini M. A cellular neural network for packet selection in a fast packet switching fabric with input buffers. IEEE Trans. On Commun., 1996; 44(12): 1649 ~ 1652 被引量:1
  • 6Itoch A. A fault-tolerant switching.network for B-ISDN. IEEE JSAC, 199 I, 9 (8) :1218- 1226. 被引量:1
  • 7Schultz K J, Gulak P G. Physical performance limits for shared buffer ATM switches. IEEE Trans. Commun. , 1997,45(8):997-1006. 被引量:1
  • 8Kozaki T, Endo N, Sakurai Y, et al. 32 × 32 shared buffer type ATM switch VLSI' s for B-ISDN. IEEE JSAC, 1991,9(8) : 1239-1247. 被引量:1
  • 9Shobatake Y, Motoyama M, Shobatake E, et al. A one-chip scalable 8 × 8 ATM switch LSI emptoying shared bulter architecture. IEEE JSAC, 1991,9(8) :1248-1254. 被引量:1
  • 10Suzuki H, Nagano H, Suzuki T. Output-buffer switch architecture for asynchronous transfer mode, Proc, of ICC' 89. 99-103. 被引量:1

引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部