摘要
本文介绍了一个高信噪比的、用在24位44.1kHz采样率的音频数/模转换器(DAC)中的4阶15级量化的delta-sigma调制器(DSM)。在设计中,为了减少量化噪声,选用了奇数个量化等级;为了提高动态范围(DR),在设计噪声传输函数(NTF)时对零点进行优化,通过这些方法降低量化噪声和时钟抖动的影响。这个DSM的峰值信噪比(SNR)可以达到130dB以上,满足0.35μmCMOS工艺设计的音频DAC的系统要求。本文给出了这个DSM的MATLAB仿真模型及仿真结果,并在此基础上给出了电路实现结构。
The paper described a four-order delta-sigma modulation （DSM） with 15 levels quantizer which was used in a 24-bit 44.1 kHz sample-rate audio digital-to-analog converter （DAC）. An odd level quantizer has been chosen instead of an even level to reduce quantization noise. To improve the DR,optimization for zero was adopted in designing NTF. These methods can reduce some influence in system. And the peak SNR of the DSM was about 130dB, which was enough for an audio DAC designed with a 0.35 μm CMOS technology. At last, the simulation results and some circuit realization were presented.
出处
《电子测量技术》
2007年第5期11-13,共3页
Electronic Measurement Technology
基金
上海市科委国际合作发展基金(055207041)资助项目
