摘要
DPA是一种非常有效的密码处理器攻击技术,它能够通过对密码处理器的功耗行为进行分析来获取密钥值。运用功耗恒定的标准单元实现密码处理器可以很好地达到防DPA攻击的目的。本文针对不同的集成电路制造工艺,分别对DDCVSL与SABL两种不同逻辑的防DPA攻击特性进行比较分析。实验结果表明,随着晶体管沟道长度的减小,内部节点电容对功耗恒定特性的作用逐渐减小,DDCVSL与SABL具有相近的防DPA攻击特性。同时,DDCVSL的功耗、延迟与面积小于SABL。
Differential-power-analysis attacks are currently the most effective on cryptographic devices. In such attacks, the power consumption of a cryptographic device is analyzed to reveal the secret key that is used inside the device. In order to counteract these attacks, DPA-resistant standard cells, instead of the static complementary CMOS standard cells, can be used to implement cryptographic devices. This paper analyzes the resistance of two different logic styles （DDCVSL and SABL） against DPA attacks in the design rules of two different process technologies. The experimental results demonstrate that DDCVSL and SABL all have a high DPA-resistance with the shrinking channel-length of the transistors. Meanwhile, the power consumption, delay and area of DDCVSL are less than those of SABL.
出处
《计算机工程与科学》
CSCD
2007年第5期19-22,36,共5页
Computer Engineering & Science
关键词
差分功耗分析
动态差分串联电压开关逻辑
灵敏放大器型逻辑
制造工艺
differential power analysis（DPA）
dynamic differential cascade voltage switch logic（DDCVSL）
sense amph-fier based logic（SABL）
process technology
