摘要
采用线性化技术改进的混频器结构提高了线性度。采用TSMC 0．18μm RF CMOS模型进行了电路仿真。仿真结果:在电源电压为1．8 V时,输入三阶截断点(IIP3)为10．3 dBm,输入1 dB压缩点(P-1dB)为-3．5 dBm,增益为9．2 dB,单边带噪声系数为17 dB。
The performance of linearity was improved using the proposed architecture. The simulation was carried out based on TSMC 0.18 μm RF CMOS model. The result shows that the supply voltage is 1.8 V, the conversion gain is 9.2 dB, input 1 dB compression point is about -3.5 dBm while IIP3 point is at 10.3 dBm, and single side-band noise figure is 17 dB.
出处
《半导体技术》
CAS
CSCD
北大核心
2007年第2期117-120,共4页
Semiconductor Technology
基金
国家973科研计划项目(51312)
