摘要
实现了一个可驱动传输线的采样时钟频率为50 MHz、精度为10位的电阻分压型数模转换器(DAC)。“dual ladder”、“best INL”矩阵式布局等新技术的采用,使得电阻串无需校正即可达到10位的精度。同时,通过运放复用技术,可在不消耗额外功耗的前提下实现阻抗匹配,并达到1.2 V的输出摆幅。该DAC在0.18μm数字CMOS工艺上得以验证实现,芯片面积为0.5 mm2,积分非线性误差(INL)为±0.45 LSB。在3.3 V电源供电、50 MHz的采样频率下,信噪失真比(SNDR)达到61 dB,功耗为55 mW。
A 10-bit 50 MHz digital-to-analog converter （DAC） is presented based on ＂dual ladder＂ resistor string and ＂best INL＂ layout techniques. By employing above techniques, the linearity and resolution requirements are satisfied without laser trimming or tuning. The output buffer is capable of driving 1.2 Vpp to 75 D load and the output impedance can match the resistive load without extra power dissipation. The DAC is fabricated in a standard CMOS digital 0. 18 tam process and it occupies a chip area of 0.5 mm^2. The measured integral nonlinearity （INL） is 0. 45 LSB. For sampling frequency up to 50 MS/s, the SNDR is better than 61 dB. The device dissipates 55 mW from a 3.3 V power supply.
出处
《微电子学》
CAS
CSCD
北大核心
2007年第2期221-225,230,共6页
Microelectronics
