摘要
为减少仿真的时间,并行仿真技术广泛应用于大规模集成电路的计算。研究发现为并行仿真所做的电路划分对提高仿真速度有相当重要的作用。该文提出一个新的多层启发式的拓扑电路划分算法,展示了将该算法应用于一个实际的电路并行仿真系统(Discovery)所获得的仿真加速。该算法主要着眼于平衡计算负载,减少整个仿真网络通信量这两方面来提高仿真系统的性能。试验结果表明该算法比其他的电路划分算法取得了更好的性能提高。
Parallel simulation techniques are often employed to meet the computational requirements of large hardware simulations in order to reduce simulation time. In addition, partitioning for parallel simulations has been shown to be vital for achieving higher simulation throughput. This paper presents the design and implementation of a new partitioning algorithm based on a multilevel heuristic, also presents the speed up of applying this to a real hardware parallel simulation system Discovery. This algorithm attempts to balance load and reduce the whole simulation network communication to improve performance. The experimental results obtained from the benchmarks indicate that this algorithm yields better partitions than other partitioning algorithms for better simulation performance.
出处
《电子与信息学报》
EI
CSCD
北大核心
2007年第4期1009-1012,共4页
Journal of Electronics & Information Technology
