摘要
提出一种基于FPGA的计算机层析重建的方法,即借助FPGA的高速数据处理能力来提高计算机层析重建的速度.采用自顶向下的方法,将FPGA依据功能划分为几个模块,并详细论述了各个模块的设计方法和控制流程.FPGA模块的设计采用VHDL语言编程和内部已有的小模块相结合的方法来实现,并利用时钟信号对模块内部以及模块之间运算和数据流程进行控制.整个软件设计和综合模拟仿真在Quartus‖开发平台中完成,同时也给出了一些模块仿真的波形.
An approach based on the high speed data handing ability of FPGA is proposed to accelerate the operation of computed tomography reconstruction algorithms. According to the method of top-down, FPGA is divided into several functional modules. The designing method and controlling flow of each module are discussed in detail in the study. VHDL language is adopted to design the PFGA modules, at the same time, many small and simple modules which have been defined in the database of VHDL are also used to build up some main and complicated modules. The operation and the flow of the data in each module or between modules are controlled by the clock signal. Software design and system simulation are completed in the integration circumstance of Quartus Ⅱ Simulating figures of some main FPGA modules have been also plotted.
出处
《光电技术应用》
2007年第1期75-80,共6页
Electro-Optic Technology Application
基金
国家自然科学基金(60577016)
