摘要
利用Altera的QuartosⅡ软件开发平台在FPGA上实现了I^2C总线IP核的设计。IP核满足I^2C总线的功能要求。主设备通过该IP核可以向从设备中写入或者从中读取数据，解决了I^2C总线在SOPC中的应用问题。为了满足复用，该IP核采用Avalon总线接口，同时利用Modelsim进行了功能仿真。
This paper is I^2C-bus IP core design which realizes in the Altera Quartus Ⅱ software development platform.Already realized the IP core of basic function, the main device can read and write data from the slave device through this IP core.In order to reuse easily ,this IP core uses the Avalon bus interface and completes the function simulation in Modelsim.
作者
栗素娟
朱清智
阎保定
LI Su-juan,ZHU Qing-zhi,YAN Bao-ding （Electronic Information Engineering College,Henan University of Science ＆ Tectmology,Luoyang 471003,China）
出处
《电脑知识与技术》
2007年第1期130-130,203,共2页
Computer Knowledge and Technology
