摘要
RS码是一种纠错能力很强的多进制BCH码,能够纠正随机错误和突发错误,广泛应用于各种差错编码中。针对不同的码型,保密通信中的首选码型为RS(31,15)码。该文分析了这种编解码方法的基本原理以及编解码算法的运算步骤,并利用Verilog硬件描述语言在FPGA硬件平台上完成了编解码实现,验证了编解码的正确性,并使用流水线技术优化设计。
As a powerful error-rectifying BCH code, RS code can rectify both random and outburst errors, and is widely applied in many error-rectifying codes, Among different code types, secret communications usually take the RS（31,15） code as their prior choice. This paper analyzed the basic principle of RS coding method and the operation steps of algorithm of code＇decode, and realized the coding/decode in the FPGA platform with Verilog HDL validate the code/decode.
