摘要
在某些工业仪表与自动化装置中，数字信号处理器经常需要与不同速度的外设芯片进行接口。在TMS320Cxx等系列DSP芯片中提供了两种机制实现与外设芯片的速度匹配：一是利用软件设置DSP内部的等待状态控制寄存器，可插入0～7个机器等待周期；二是提供READY信号管脚，由外部电路控制可以产生任意数目的等待周期。本文应用CPLD分别采用图形输入法和VHDL语言编程产生等待信号，实现了DSP与外设芯片的速度匹配，简化了DSP访问外设时由软件产生等待的程序编写，提高了整个系统的执行速度。
In some industry instrument and aulomation equipment, the digital signal processor（DSP） usually needs establishing the interface with different speed peripheral chips. TMS320Cxx provide two kinds of mechanism to match with outside chips. One can insert 0- 7 wait periods by setting inner control register. Another is to provide the READY signal pin, it can produce arbitrarily number of wait period with the exterior control circuit. In this paper CPLD is employed to generate the waiting sign by the correlative hardware circuit diagram and VHDI. language programs method respectively. The speed match circuits have been realized between DSP and peripheral chips. It can simplify the program and raise the whole performance speed of system.
出处
《电子测量技术》
2006年第4期73-75,共3页
Electronic Measurement Technology
