摘要
位于Ｓｉ／ＳｉＯ２界面附近的具有长时间常数的载流子陷阱对于半导体器件的可靠性有重要影响．根据笔者建立的双极晶体管表面１／ｆ噪声分析模型，通过测量栅控晶体管１／ｆ噪声的栅压特性，可获得这种慢界面陷阱密度在禁带中心附近的能量分布．本文给出了该方法的模型推导、参数提取、分析步骤和应用实例．
Abstract The slow carrier traps near Si/SiO2 interface have an impact on reliability in semiconductor devices. Based on an analytical model of the surface 1/f noise in bipolar transistors developed in this paper, the energy distribution of the slow interface trap is determined by means of the measured 1/f noise variation with gate voltage for the gate-controlled transistor. The analysis procedure and example are presented.EEACC: 2560J, 2530F, 7320C
关键词
双极型器件
界面陷阱
1/f噪声
Acoustic noise
Energy dissipation
Interfaces (materials)
Semiconductor devices
