摘要
针对可编程逻辑器件中组合逻辑电路的优化设计问题,依据复杂网络理论中小世界模型分簇的基本特征,提出了双重优化设计指标下的电路设计方法,以16位奇偶校验电路为例,利用Matlab对电路进行了仿真。仿真结果表明,通过适当降低网络分簇度,有效削弱关键节点在电路中的作用,并适当增加网络连接的冗余性,避免关键元器件的故障导致整个系统的灾害性失败的现象出现,从而降低电路的脆弱性,提高电路鲁棒性和可靠性。
For optimization design of combinatorial logic circuit of programmable logic device, the design method of circuit is presented based on double-optimization index according to basic characteristic of small-world model clustering of complex network. Using 16 bit parity circuit as an example which is simu- lated using Matlab. Simulation results prove that the method weakens function of key node in circuit effectively by reducing network clustering properly, and avoid the phenomenon that fault of key component leads to catastrophic failure of the whole system by enhancing redundancy of network connections properly, thus, reduct frangibility and improve robustness and reliability of circuit.
出处
《电机与控制学报》
EI
CSCD
北大核心
2006年第4期370-374,共5页
Electric Machines and Control
关键词
小世界网络模型
平均分布度
分簇系数
平均路径长度
small-world network model
average degree of distribution
clustering coefficient
average path length
