摘要
介绍了I^2C总线协议及基于FPGA芯片的I^2C总线接口结构框图．提出了复杂时序电路状态机嵌套的设计思想,并给出了基于Verilog HDL的I^2C总线接口电路的硬件描述．在ISE 6．1i平台下结合ModelSim SE 5．7进行了设计仿真,实现了XC2S100对I^2C总线器件的读写操作．
The protocol and principle of I^2C Bus were introduced. The framework of I^2C-Bus based on FPGA was proposed. The idea of nesting state-machine of complicated timing-circuit and the hardware description of I^2C-Bus interface by Verilog HDL were presented. The simulation of designing under the Xilinx ISE 6.1 i development platform combined with ModelSim SE 5.7 was made and the operation on I^2C device based on Spartan Ⅱ XC2S100 was implemented.
出处
《华东师范大学学报（自然科学版）》
CAS
CSCD
北大核心
2006年第4期11-15,共5页
Journal of East China Normal University(Natural Science)
基金
上海市科委AM基金(D206)
