期刊文献+

新型全差分电荷泵设计 被引量:5

Design of Novel Fully-differential Charge Pump
下载PDF
导出
摘要 采用差分输入和差分输出方案,设计了一种新型的全差分电荷泵。采用差分输出不仅能够降低电荷泄漏所带来的电压噪声,而且能够提高电荷泵的上升和下降速度,从而提高锁相环的工作速度,还能增大输出电压的范围。在差分输入端,采用正反馈电路结构,以提高开启和关断速度,并降低功耗。上拉泵电路和下拉泵电路完全对称,能够消除电流失配所带来的噪声。 A new novel fully-differential charge pump was designed in this paper, differential input and differential output was used in this circuit. The differential output circuit not only reduced the voltage noise created by leakage current, but also increased the ascending/descending speed to improve the speed of PLL further and enlarged the range of output voltage. In the differential input, positive feedback circuit was used to increase the switching speed and attain low power. The circuits of pump-up and pump-down are symmetric to overcome the disadvantage of charge/discharge current mismatches.
出处 《微电子学与计算机》 CSCD 北大核心 2006年第7期134-136,139,共4页 Microelectronics & Computer
基金 湖南省自然科学基金项目(05JJ30115)
关键词 电荷泵 大摆幅电流镜 差分输入输出 数字锁相环 Charge pump, Wide-swing current mirror, Differential input and output, DPLL
  • 相关文献

参考文献7

  • 1Terlemez,B Uyemura,J P.The design of a differential CMOS charge pump for high performance phase-locked loops.circuits and systems,2004,4:23~26 被引量:1
  • 2Robert C Chang,Lung-Chih kuo.A new low-voltage charge pump circuit for PLL.IEEE,ISCAS 2000-IEEE International symposium on circuits and systems,2000,701~704 被引量:1
  • 3LinYijing.ShengShimin,A novel charge pump in PLL[J].北京大学学报:自然科学版,2002,38(3):284-386. 被引量:2
  • 4袁小云,张瑞智,王洪娜.一种新型电荷泵电路的设计[J].微电子学与计算机,2003,20(9):69-72. 被引量:10
  • 5Chang R C,Lung-Chih Kuo.A new low-voltage charge pump circuit for PLL.Circuits and Systems,2000.Proceedings.ISCAS 2000 Geneva.2000,5:701~704 被引量:1
  • 6李金城,仇玉林.Current Mismatches in Charge Pumps of DLL-Based RF CMOS Oscillators[J].Journal of Semiconductors,2001,22(11):1369-1373. 被引量:1
  • 7Chi-Chang Wang,Jin-chuan Wu.Efficiency improvement in charge pump circuits.IEEE journal of solid-state circuits,1997,32(6):852~860 被引量:1

二级参考文献6

  • 1王福昌 鲁昆生.锁相技术[M].武汉:华中理工大学出版社,1996.. 被引量:5
  • 2VAN PAEMEL, M. Analysis of a Charge Pump PLL: new Model. IEEE, 1994, 2490-2498. 被引量:1
  • 3Jae-Shin Lee, Min-Sun Keel. Charge Pump with Perfect Current Matching Characteristics in Phase Locked Loops.Electronics Letters, 2000, 36, 1907-1908. 被引量:1
  • 4Robert C Chang and Lung-Chih Kuo. A New Low-voltage Charge Pump Circuit for PLL IEEE, 2000, 701-704. 被引量:1
  • 5Woogeun Rhee. Design of High-performance CMOS Charge Pumps in Phased-locked Loops. IEEE, 1999, 545-548. 被引量:1
  • 6郑君里,信号与系统(上册),1991年 被引量:1

共引文献10

同被引文献27

  • 1杨文荣,曹家麟,冉峰,王键,秦霆镐.一种适用于RF频率合成器的CMOS高速双模前置分频器[J].上海大学学报(自然科学版),2005,11(1):20-23. 被引量:5
  • 2王烜,来金梅,孙承绶,章倩苓.用于高速PLL的CMOS电荷泵电路[J].复旦学报(自然科学版),2005,44(6):929-934. 被引量:13
  • 3汪猛,丁瑞雪,杨银堂.一种2.4G的低功耗BiCMOS预置数分频器[J].微电子学与计算机,2006,23(3):169-171. 被引量:3
  • 4Rhee W. Design of high- performance CMOS charge pumps in phaselocked loops[J]. IEEE proceedings of the International symposium on Circuits and Systems, 1999 (1) : 545 - 548. 被引量:1
  • 5Lee J, Keel M, Kim S. Charge pump with perfect current matching characteristics in phase- locked loops [ J ]. Electronics Letters, 2000,36(23) :1907- 1908. 被引量:1
  • 6Choi Y S, I-Ian D H. Gain- bossting charge pump for current matching in phase- locked loop [ J ]. IEEE Transactions on Circuits and Systems, 2006,53 (10) : 1022 - 1025. 被引量:1
  • 7Razavi B. Design of analog CMOS integrated circuits [M]. Beijing: Publishing house of Tsinghua University, 2005. 被引量:1
  • 8毕查德·拉扎维.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2002. 被引量:34
  • 9Foroudi N,Kwasniewski T A.CMOS high speed dualmodulus frequency divider for RF frequency synthesis[J].IEEE Journal of Solid-state Circuits,1995,30 (2):93~100 被引量:1
  • 10Ullas Singh,Michael Green.New structures for very highfrequency CMOS clock dividers[J].Circuits and Systems,2001.ISCAS 2001.The 2001 IEEE International Symposium on Sept,2001,4:622~625 被引量:1

引证文献5

二级引证文献8

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部