摘要
针对S i/S iG e p-M O SFET的虚拟S iG e衬底厚度较大(大于1μm)的问题,采用低温S i技术在S i缓冲层和虚拟S iG e衬底之间M BE生长低温-S i层。S iG e层应力通过低温-S i层释放,达到应变弛豫。XRD和AFM测试表明,S i0.8G e0.2层厚度可减薄至300 nm,其弛豫度大于85%,表面平均粗糙度仅为1.02 nm。试制出应变S i/S iG e p-M O SFET器件,最大空穴迁移率达到112 cm2/V s,其性能略优于目前多采用1μm厚虚拟S iG e衬底的器件。
SiGe virtual substrate in Si/SiGe P-type field-effect transistors （p-MOSFET） is always too thick（〉1 μm）. To solve this problem, a low-temperature Si layer grown by MBE is introduced between Si buffer and SiGe layer. The strain in SiGe layer can be relaxed through LT Si layer. The tests of XRD and AFM show that the thickness of SiGe layer can be reduced to 300 nm, the strain relaxation degree exceeds 85%, RMS roughness is less than 1.02 nm. The fabricated transistors performance is better than that of devices achieved on thick SiGe virtual substrate layer. The hole mobility can reach 112 cm^2/Vs.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2006年第2期162-165,共4页
Research & Progress of SSE
基金
重点实验室基金(2000JS09.3.1.DZ02)资助
