摘要
传统的多输入浮点乘法运算是通过级联二输入浮点乘法器来实现的,这种结构不可避免地使运算时延和所需逻辑资源成倍增加,从而难以满足高速数字信号处理的需求。本文提出了一种适合于在FPGA上实现的浮点数据格式和可以在三级流水线内完成的一种高效的多输入浮点乘法器结构,并给出了在Xilinx公司Virtex系列芯片上的测试数据。
Multiple-input floating-point multiplier is usually composed of several double-input floating-point muhipliers,and it＇s inevitable to increase logic resource and processing latency,which makes it harder and harder to meet the requirement of high-speed digital signal processing.This article puts forward a new kind of floating-point format fitting for implementation on FPGA and a sort of high performance structure with which calculating within three clock cycles can be completed.Test data is presented at the end of this article.
出处
《计算机工程与应用》
CSCD
北大核心
2006年第10期103-104,共2页
Computer Engineering and Applications
关键词
浮点乘法器
多输入
FPGA
高效算法
floating-point multiplier,multiple input,FPGA,high-speed algorithm
