摘要
在硬件设计的初期可以对硬件测试中条件分支结构引起的测试向量冗余问题加以解决.以ALU为例,提出了两种分支结构电路的可测性优化设计,通过调整分支电路的选择条件来控制测试向量的施加,在保证错误覆盖率的同时可以明显减少不必要的测试向量.
Testability problems can be treated at the early stage of design cycle. Two optimized methods for DFT design are presented. The number of test patterns for multiple conditional branches can be controlled. As a result, the redundancy of the test patterns can be greatly improved without lowing fault coverage.
出处
《复旦学报（自然科学版）》
CAS
CSCD
北大核心
2006年第1期92-95,101,共5页
Journal of Fudan University：Natural Science
