摘要
数字乘法器是目前数字信号处理中运用最广泛的执行部件之一,本文设计了三种基于FPGA的数字乘法器,分别是移位相加乘法器、加法器树乘法器和移位相加—加法器树混合乘法器。通过对三种方案的仿真综合以及速度和面积的比较指出了混合乘法器是其中最佳的设计方案。
The digital multiplier is used as one of the most extensive execution parts while digital signal processing at present.This text has designed three kinds of digital multipliers based on FPGA,they are shift summation multiplier,addition device tree multiplier and shift summation-addition device tree mixed multiplier.Through the simulation-synthesizing of the three kinds of schemes and comparing the speed with the area,we has pointed that the mixed multiplier is the best design method among them.
出处
《电脑知识与技术》
2006年第2期122-123,共2页
Computer Knowledge and Technology
