摘要
提出了一种新的基于并行的(6,10)小波变换的提升算法及其一维结构的优化设计。利用并行的提升方案实现了小波变换各提升步中乘法运算的并行计算,达到了有效缩短其结构关键路径的目的;运用并行的提升技术构造了一种前向和逆向小波变换的统一形式,从而给出了一种有效的小波前向和逆向变换的可配置结构。采用重调度技术进一步优化了小波变换的一维结构,在关键路径的约束条件下有效节省了硬件资源。采用Altera的FPGA器件EP1S25F1020C6对设计的VerilogHDL模型进行了逻辑综合。综合结果显示,新结构的关键路径、占用逻辑单元和触发器单元比同类设计分别减少了约14.2%,7.8%和12.5%,有效提高了系统的工作频率和降低了系统的硬件资源需求。
A novel parallel-based lifting scheme （PLS） for the （6,10） discrete wavelet transform （DWT） and its optimal I-D architecture were presented. The proposed PLS achieves parallel computation of multiplication operations used in all lifting steps, which leads to shortening the critical path efficiently. An equal formulation for forward and inverse DWT could be obtained using the PLS, providing an efficient reconfigurable architecture for them. Retiming technique was employed to further optimize design of I-D architecture, which saved considerably the hardware resources under the tight critical path The Verilog HDL model for the design is synthesized into Altera＇s FPGA device EP1S25F1020C6. Synthesis results show that, the critical path, the occupied logic cell and flip-flops for the proposed architecture are respectively reduced by about 14.2%, 7.8% and 12.5% compared with the similar work, which efficiently increases working frequency and reduces hardware cost of device. The presented approach could be generalized to the optimal design of architecture for other wavelet filters.
出处
《光电工程》
EI
CAS
CSCD
北大核心
2006年第1期94-97,共4页
Opto-Electronic Engineering
基金
国家863计划项目基金
关键词
离散小波变换
优化设计
结构设计
并行算法
VLSI
Discrete wavelet transform
Optimize design
Structural design
Parallel computing
VLSI
