摘要
现代高性能FPGA和DSP的不断出现,使得需要大数据量计算的雷达信号处理器向高度集成化和小型化方向发展成为可能,本文基于高性能FPGA(A ltera的Stratix II系列)详细介绍了一种数字波束形成器(DBF)、动目标检测器(MTD)和恒虚警检测器(CFAR)的单芯片集成设计方案,最后对其性能特性和改进方向做了初步的分析讨论,以满足更高性能要求时的设计实现。
With the modern powerful FPGA and DSP emerged in multitude, it＇s possible to design Radar Signal Processor that involves mass calculation towards integration and miniaturization. This paper gives an introduction of a FPGA -based single chip （Altera Stratix II series） design which integrated Digital Beamformer, Moving Target Detector and Constant False Alarm detector; furthermore, it discusses the characteristic and improvement of the design for meeting more complex arithmetic implement.
出处
《航空计算技术》
2005年第4期38-41,共4页
Aeronautical Computing Technique
