摘要
研究JPEG 2000标准中系数位平面编码的硬件实现问题,提出一种适合ASIC实现的结构,在保证编码速度的前提下,最大限度减小了片内小波系数缓存量,解决了扫描过程中如何对系数状态字进行读写的问题,大大减少了系统访问系数状态字的频率。设计中幅度细通道和清理通道并行工作,使编码时间比传统非并行工作减少30%以上。在FPGA上对设计进行了仿真验证。
FPGA implementation of the bit-plane coding in JPEG 2000 standard is studied in the paper. A architecture suitable for ASIC implementation is proposed ,which greatly speeds up the coding process and achieves higher hardware utilization, solve the problem how to read and write the coefficient state words in the RAMS, and decreases the frequency of the system to visit the coefficient state words in the RAMS. In this paper, cleanup pass works concurrently with magnitude refinement pass, which reduces the processing time by more than 30% compared with the conventional design. The design is simulated and verified on FPGA.
出处
《计算机应用研究》
CSCD
北大核心
2005年第10期157-161,共5页
Application Research of Computers
基金
中国人民解放军总装备部预研项目(413160601)
"十五"国防基础微电子预研项目(41308010408)
