摘要
本文提出了一种基于组的时序驱动布局规划方法,它利用现有的EDA工具将网表划分为组,并充分利用设计师的体系结构经验进行布局、调整和优化。该方法能在设计早期获取较为准确的线负载模型,提高前端与后端的一致性,并且可以以组为单位规划电源和地的布局,提高布通率。该方法在已研制成功的32位嵌入式微处理器Estar的物理设计中得到实际应用。结果表明,该方法能够有效地改善关键路径时序和加快设计进程。
This paper proposes a timing-driven floorplan method based on groups in the physical design. This method employs available EDA tools and partitions the netlist into groups, and then utilizes the architecture experience of designers to layout, adjust and optimize the netlist. This method can backarmotate the better custom wire load model to the synthesis and improve the consistency between the synthesis and layout. This method can also distribute the power and ground network based on groups and make it easy to route successfully. The experimental results on a 32 bits microprocessor, which has been tapouted successfully, show that the method can improve the timing of critical paths and accelerate the process of physical design.
出处
《计算机工程与科学》
CSCD
2005年第9期100-104,共5页
Computer Engineering & Science
基金
国家自然科学基金资助项目(90207019)
国家863计划资助项目(2002AA1Z1480)
