摘要
阻塞与非阻塞过程赋值在Verilog语言中是最容易混淆的两种结构,正确理解两者在仿真和综合中的区别是很困难的。阻塞与非阻塞过程赋值的误用不仅在仿真时会产生一些逻辑错误,而且会造成仿真与综合的不一致,更为严重的是往往这种错误不易被发现。为解决这一问题,必须深刻理解阻塞与非阻塞过程赋值的功能和执行过程的本质区别。并在此基础上运用一些可以产生可综合逻辑并能避免仿真错误的重要的编码风格,才可以有效地避免阻塞与非阻塞过程赋值的误用。
Blocking and nonblocking assignments are the most easily confusing two structures in Verilog HDL language. When they are simulated and synthesized,it＇s very difficult to understand the differences between them accurately. The misusing of the blocking and nonblocking assignments not only brings some logical mistakes ,but also leads to the disagreements between the results of the simulation and synthesis. And the more serious thing is these mistakes cannot be found easily. To solve these problems, comprehending the functions and the execution processes of the blocking and nonblocking assignments profoundly is necessary. Based on the comprehending, utilizing some important coding styles which can create synthetical logics and avoid the mistakes in the simulation. Thus it can be avoided efficiently to misuse blocking and nonblocking assignments.
出处
《现代电子技术》
2005年第18期99-101,共3页
Modern Electronics Technique
