摘要
针对MPEG-4编解码中运动补偿控制复杂、数据吞吐量大、实现较困难的特点,提出了一种适合MPEG-4的运动补偿硬件实现方案,解决了时序分配、输入输出控制等较难处理的问题。文中的方案已经在XilinxISE6.1i集成开发环境下,采用了VHDL进行描述,并使用了电子设计自动化(EDA)工具进行了模拟和验证。仿真和综合结果表明,该处理器逻辑功能完全正确,能满足MPEG-4CoreProfiles&Level2实时编码要求,可用于MPEG-4的VLSI实现。
In the light of complex control, high throughput and difficult implementation of motion compensation of MPEG-4 decoding, a motion compensation （MC） circuit solving the timing and I/O of decoding was presented for MPEG-4. The VLSI architecture and implementation in terms of VHDL are designed in the Xilinx ISE6.1i environment and some simulations are carried out in tools of electronic design automation （EDA）. The experimental results show that the VLSI processor designed can perform correct logic functions and can achieve a real-time coding for MPEG-4 Core Profile and Level 2.
出处
《电子器件》
EI
CAS
2005年第3期546-550,共5页
Chinese Journal of Electron Devices
关键词
超大规模集成电路
MPEG-4
运动补偿
very large scale integrated circuit （VLSI）
MPEG-4
motion compensation
