摘要
在0.18μm下,时序收敛的关键是互连线延时问题。文章介绍了一种时序快速收敛的RTL到GDSII的设计方法,该方法有效地消除了逻辑综合和物理设计之间的迭代。采用一个450万门超大规模DSP芯片设计验证了该方法。实例设计结果表明,这种新的方法不但有效地解决了互连线时延的问题,而且缩短了芯片的设计周期。
In deep submicron technology, the key to timing convergence is the wire delay. This paper presents a design method from RTL to GDSII, which can get fast timing convergence and eliminate iterations between physical design and logic synthesis. The method is verified by designing a 4.5 million gate DSP chip.The design example demonstrates that the new method efficiently solves the interconnect delay problem and shortens the design cycle.
出处
《微电子学》
CAS
CSCD
北大核心
2005年第3期283-285,289,共4页
Microelectronics
