摘要
设计异步集成电路时,常用的异步标准单元的分类、电路设计方法和电路结构.详细介绍了C单元和异步数据通路的设计与实现,提出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路.利用设计的异步标准单元构成了一个适用于Viterbi解码器的异步ACS(加法器-比较器-选择器),并通过0.6μmCMOS工艺进行投片验证.当芯片工作电压为5V,工作频率为20MHz时的功耗为75.5mW.芯片的平均响应时间为19.18ns,仅为最差响应时间23.37ns的82%.从而验证了异步标准单元的正确性和异步电路在性能方面较同步电路存在的优势.
The categories, circuits design method and architectures for asynchronous standard cells are described. The design and implementation of C element and asynchronous data-path are introduced The circuits of asynchronous adder unit, asynchronous comparator unit, and asynchronous selector unit are proposed. Using these standard cells, an asynchronous ACS (Add-Compare-Select) processor for Viterbi decoder is formed. It has been fabricated in 0.6 μ m CMOS process. At a supply voltage of 5 V, when it operates at 20 MHz, the power consumption is 75.5 mW. The results of performance test of asynchronous 4 bit ACS processor show that the average case response time 19.18 ns is only 82% the worst-case response time 23.37 ns. The correctness of asynchronous standard cells has been proved. It reveals that the asynchronous circuits have some performance advantages than the synchronous ones.
出处
《电子器件》
EI
CAS
2005年第2期346-348,351,共4页
Chinese Journal of Electron Devices
基金
国家自然科学基金资助项目(编号:60076017
90307004)
