摘要
讨论了基于滑窗MAX-LOG-MAP算法的Turbo码译码器的FPGA实现方案。采用基于流水线和多时钟的设计,提高了译码速度,同时在对算法流程分析基础上,通过优化设计,减少了译码所需的存储量。整个设计用VHDL语言描述,并在Altera公司的Cyclone系列上得到了实现。
In this paper, the implementation scheme of Turbo decoder based on FPGA is discussed by using MAX-LOG-MAP algorithm coupled with slid window algorithm. The latency of decoding process is reduced by using pipeline and multi-clock. Based on the analysis of algorithm procedure, some optimized designs are introduced to cut down the requirement of memory. The whole design is described with VHDL and implemented successfully on the Cyclone series of Altera.
出处
《北京电子科技学院学报》
2004年第4期47-51,共5页
Journal of Beijing Electronic Science And Technology Institute
