摘要
基于RLC互连树节点导纳的低阶矩构建了一种稳定的互连π模型,并讨论了它在互连树延时和逻辑门延时估计中的应用.结果表明,该模型与已有方法相比精度有一定程度的提高.
This paper constructs a stable RLC interconnect π model based on the first three moments of the node admittance,and discusses its application to interconnect delay and logic gate delay estimation.Results show that the accuracy is considerably increased compared with the methods available.
基金
国防科技预研资助项目(No.41323020204)~~
关键词
RLC互连树
节点导纳
逻辑门
延时
RLC interconnect tree
node admittance
logic gate
delay
