摘要
设计了一种基于CORDIC算法的正交输出直接数学频率合成器(QDDS),并在ALTERA FLEX10K 系列FPGA上予以实现.该结构包括流水线32位相位累加器和16位CORDIC旋转器.系统的时钟频率20M Hz,频率切换器时为一个时钟,建立时间为20个时钟,频率为0.004 656 Hz,输出信号的频率为DC到8M Hz.
A Quadrature Direct Digital Frequency Synthesizer (QDDS) based on CORDIC algorithm is presented. This architecture consisted of pzpelined 32-bit phase accumulator and a 16-bit CORDIC rotator, is implemented with ALTERA FLEX 10K FPGA. The system clock is 20MHz, the frequency-switching time is one clock cycle, the tuning latency is 20 clock cycle, frequency resolution is 0. 004 6 Hz. Output frequency rang from dcto 8M Hz.
出处
《南开大学学报（自然科学版）》
CAS
CSCD
北大核心
2005年第1期60-64,共5页
Acta Scientiarum Naturalium Universitatis Nankaiensis
基金
天津市重点攻关资助项目(033187111)
