摘要
介绍了基于高速的AD、DA,以及大容量FIFO的数字延迟线硬件和软件设计方法。阐述了一种总延迟时间长、延迟步长时间短,且延迟时间控制灵活的数字延迟线设计思路和方法,同时对设计中的关键问题进行了理论阐述和推导。
Based on the high-speed ADC and the great capacity FIFO, the design method of hardware and soft- ware for digital delay line is introduced. The design ideas for the digital delay line are presented, which has long total delay time, short step delay and flexible controlling method.
出处
《测控技术》
CSCD
2005年第4期72-74,共3页
Measurement & Control Technology
关键词
数字延迟线
高速数字电路
模数转换器
digital delay line
high-speed digital circuit
A/D converter
