摘要
针对宽带正交频分复用(OFDM)系统中高速数据处理的要求,提出了 64 点高速定点快速傅立叶变换(FFT)处理器在现场可编程门阵列(FPGA)中的设计与实现方法.该方法采用了基于按频率抽取(DIF)Radix 4 算法的3级流水线结构,每级将乘法器的旋转因子输入端固定为常数值,而不是作为变量从ROM中读取,流水寄存中间数据结果,使之处于稳态,并进行比特位截取定点操作.实验结果表明,该方法在保证运算精度和实现复杂度的同时,减少了ROM读取时间,提高了处理器的数据时钟频率和处理速度,更好的满足了宽带 OFDM系统高速数据收发处理的要求.
To meet the requirement of high data processing rate in broad band orthogonal frequency division multiplexing (OFDM) system, an implementation method of 64 points fixed-point high rate fast Fourier transform (FFT) processor in field programmable gate array (FPGA) was discussed. Based on decimate in frequency (DIF) Radix-4 algorithm, a 3 levels pipeline structure was adopted. In each level, the rotating factor inputs of multipliers were fixed to constants but not variables read from ROM. Intermediate datum were registered with pipeline function to be steady states, and bits were truncated according to the fixed-point operate principle. Experimental results show that under prerequisite of accuracy and complexity, the method reduces the time for reading data from ROM, improves the operating clock and processing rate, and guarantees high speed data processing in broad band OFDM.
出处
《浙江大学学报（工学版）》
EI
CAS
CSCD
北大核心
2005年第3期407-413,共7页
Journal of Zhejiang University：Engineering Science
基金
国家自然科学基金资助项目(60002003)
国家"863"高技术研究发展计划资助项目(2002AA123044).
关键词
正交频分复用
快速傅立叶变换
按频率抽取
流水线
Fast Fourier transforms
Field programmable gate arrays
Parallel processing systems
Pipeline processing systems
Program processors
