摘要
SystemC在软硬件协同设计中发挥着越来越重要的作用,而如何把SystemC的描述的模型转换成可综合的HDL代码已经成为软硬件协同设计的关键问题。文中提出把SystemC的数据类型转换成综合的VHDL代码的方法,并利用这种方法把一个SystemC语言描述的三态门模型转换成可综合的VHDL代码。此方法为IC设计者开发SystemC到可综合的VHDL代码的转换工具提供了一种思路,具有实用价值。
SystemC plays more and more importance in hard ware and software codesign. And how to translate SystemC code to synthesizable HDL description is becoming a key problem in SystemC application A technique of translating SystemC data type to synthesizable VHDL code is presented in this paper. And the presented method is used to transform SystemC to VHDL for a three--state gate mode.This method can give IC designers an idea to develop a tool to translate systemC code to synthesizable VHDL one. The presented method has utilized value.
出处
《电子测量技术》
2005年第1期63-64,共2页
Electronic Measurement Technology
