摘要
本文为ＦＨ／ＤＳ系统提出了一种快速数字销相的位同步方案，给出了该方案的构造原理及实现方法，并对系统的同步概率进行了理论分析，最后给出了实验结果，该方案的抗干扰能力优于传统方案。
In the paper,a schem of bit synchronization named 'fast phase lock' for FH/DS communication system is proposed. The theory and realization of this schem are given,the probability of the synchronization of this schem has been analysed. The results of the experiment are given. The synchronization performance of this schem is better than that of the traditional schem in respect of the anti-interference ability.
出处
《电讯技术》
北大核心
1994年第2期16-21,共6页
Telecommunication Engineering
关键词
数字通信
锁相环
位同步
Digital Communications,PLL, Bit Synchronization
