摘要
本文阐述一种由片内二进制计数与“异或”门阵列组成的内装测试电路产生测试模式的新方法。根据线性变换的基本原理对电路设计的“异或”门阵列进一步简化,可以实现在有限的硬件支持下达到预期故障覆盖率的效果,从而促进了内装测试技术的推广和应用。
A new method of on chip tert pattern in buit-in selt-terting formed by a binary Counter and XOR gates is discussed.The designed array can be simplified with linear algebraic synthesis By this approach,a Considerable limited hardware can achieve a good fault coverage and promote the applatiicon of built-in self-testing technique.
出处
《计算机研究与发展》
EI
CSCD
北大核心
1993年第11期61-65,F004,共6页
Journal of Computer Research and Development
关键词
集成电路
VLSI
测试
test pattern
fault covering
built-in self-testing
test sequence.
