摘要
针对SoC设计中的时间瓶颈,利用SystemC设计语言根据AMBA规范建立了事务级总线模型,并将MP3解码器和控制器作为主设备接入该模型,验证本模型的可用性与有效性,试验结果表明该模型可以有效地在系统层次对SoC芯片的集成进行设计验证,加快SoC系统的设计速度,且能做到时钟精确。
Aiming at time bottleneck ,a method of modeling SoC transaction level bus model ,which is based on AMBA specification using SystenC ,is introduced in this paper. Attaching MP3 decoder and controller, as master module, to it not only can be an instance for verification ,but prove to be usable and valid of this model .All this clarify that this model can design and verify the integration of SoC chip in system level validly , improve the design speed of SoC system and be a cycle-based simulator.
出处
《微电子学与计算机》
CSCD
北大核心
2004年第12期1-3,8,共4页
Microelectronics & Computer
基金
国家863计划项目资助(2002AA1Z1490)
