期刊文献+

SoC及其IP核的设计与其在通信中的应用研究 被引量:3

Application of SoC and IP cores design and its application in communications
下载PDF
导出
摘要 提出现代集成电路技术中的SoC及其IP核的设计方法,在分析SoC的特点及其IP核的基本特征的基础上,给出了系统级设计软件、IP核开发流程和关键技术,并将其应用于NGN中综合业务接入系统的具有自主知识产权的集成电路设计中. The design methodology of SoC and IP cores is described. Based on the analysis of characteristics of SoC and IP cores the system level design software is introduced, and the design flow of IP cores and the key technology of SoC and IP cores are provided. The design in integrated access system IC using the above methods is also point out.
出处 《天津工业大学学报》 CAS 2005年第1期59-63,共5页 Journal of Tiangong University
基金 天津市高等学校科技发展基金资助项目(020712).
关键词 片上系统 IP核 系统级设计 设计流程 SoC IP cores system level design design flow
  • 相关文献

参考文献7

  • 1陆盘峰,魏少军.SOC设计方法学和可测试性设计研究进展[J].微电子学,2004,34(3):235-240. 被引量:6
  • 2杨焱,侯朝焕.一种面向系统芯片的FPGA协同验证方法[J].微电子学,2004,34(4):469-472. 被引量:3
  • 3Bhattacharya S. Transformation and re-synthesis for testability of RT-Level control data path specification [J]. IEEE Trans VLSI, 1993,1 (3) :304 - 318. 被引量:1
  • 4Whetsel L. Core test connectivity , communication&control [A]. Proc IEEE Int Test Conf[ C]. Washington DC: IEEE Computer Society Press, 1998. 303 - 312. 被引量:1
  • 5Marinissen J E, Zorian Y. Challenges in testing core-based System ICs [J]. IEEE Communications Magazine, 1999,37(6) :104 - 109. 被引量:1
  • 6Zorian Y, Marinissen E J, Dey S. Testing embedded-corebased System chips [J] . IEEE Computer, 1999,32 (6): 52- 60. 被引量:1
  • 7Zorian Y. Test requirements for embedded core-based Systems and IEEE P1S00[A]. Proc IEEE Int Test Conf[C].Los Alamitos,CA: IEEE Computer Society Press, 1997. 191- 199. 被引量:1

二级参考文献15

  • 1Anderson T. This is hard core[J]. Test -The European Test Industry Journal, 1999; 25(5): S-5-6. 被引量:1
  • 2Zorian Y, Marinissen E J, Dey S. Testing embeddedcore-based system chips[J]. IEEE Computer, 1999;32(6):52-60. 被引量:1
  • 3Zorian Y. Test requirements for embedded core-based systems and IEEE P1500[A]. Proc IEEE Int Test Conf[C]. IEEE Computer Society Press, Los Alamitos, CA:1997.191-199. 被引量:1
  • 4Marinissen J E, Zorian Y. Challenges in testing corebased system ICs[J]. IEEE Communications Magazine, 1999; 37(6): 104-109. 被引量:1
  • 5Whetsel L. Core test connectivity, communication &control[A]. Proc IEEE Int Test Conf[C]. Washington, DC: IEEE Computer Society Press, 1998. 303-312. 被引量:1
  • 6Avra L J, McCluskey E J. High level synthesis of testable design[A]. Test Synthesis Seminar, Proc IEEE Int Test Conf[C]. 1994. 被引量:1
  • 7Potkonjak M S. Behavioral synthesis of area efficient testable design using interconnection between hardware sharing and partial scan[J]. IEEE Trans CAD,1995; 14(9): 1141-1154. 被引量:1
  • 8Bhattacharya S. Transformation and re-synthesis for testability of RT-Level control data path specification[J]. IEEE Trans VLSI, 1993;1(3): 304-318. 被引量:1
  • 9Heragu K. Improving a nonenumerative method to estimate path delay fault coverage [J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 1997; 16(6) :759-762. 被引量:1
  • 10Naseer A R, Balakrishnam, Kumar A. Direct mapping of RTL structures onto LUT-based FPGA' s[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 1998; 17(7):624-630. 被引量:1

共引文献7

同被引文献27

引证文献3

二级引证文献15

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部