摘要
设计了一种数字移相分频钟 ,其中利用了先进的复杂可编程逻辑器件(CPLD -ComplexProgrammableLogicDevice)技术 ,将硬件电路模块化 ,把各功能模块集成在一个芯片中。与以往用分立元件设计硬件电路相比 ,具有电路简单 ,可靠性高 。
A digital phase-shifting frequency-dividing clock has been designed with CPLD(Complex Programmable Logic Device) technique which modularizes hardware circuit and integrates different modules into one chip.Compared with original circuit designed with separate components this design is characterized by simple hardware circuit and high reliability,and is easy to be debugged.
出处
《时间频率学报》
CSCD
2004年第1期1-7,共7页
Journal of Time and Frequency
关键词
CPLD
数字移相分频钟
电路设计
工作原理
complex programmable logic device(CPLD)
digital phase-shifting frequency-dividing clock
