摘要
采用0.6 μm CMOS工艺设计了AES加密模块的串行接口单元电路,提高了AES加密芯片的数据吞吐量。 基于CMOS互补逻辑的电路结构降低了的功耗,实现了与核心电路的电平匹配。全定制的设计方法优化了电路性 能和版图面积,提高了设计可靠性,降低了研究成本。
In order to achieve high throughput rate of the circuit, which implemented the AES (Advanced Encryption Standard) algorithm, an interface circuit based on 0. 6μm CMOS technology was designed. The low power consumption was obtained by using CMOS complementary logic. The full custom layout design saved the area of the chip and reduced the cost.
基金
南通工学院自然科学基金资助项目(院自200340)
