摘要
针对嵌入式实时软件需求规约及其检测问题,提出了基于层次并发有穷状态机的可合成的图形化建模语言RTRSM*(real-time requirements specification model*),利用转换有效期和事件预定机制来描述时间限制,能够较好地支持系统交互性和实时性的建模.为弥补RTRSM*作为操作性规约语言不便于性质描述的问题,提出了命题时序逻辑RITL(real-time interval temporal logic).该语言以时间状态序列为语义模型,具有基于区间和时间点的量化时间属性描述功能,能自然、全面地描述RTRSM*模型性质.介绍并讨论了基于两种语言的规约检测方法和技术,主要包括系统状态空间有穷的RTRSM*模型状态可达图的相关问题和规约的模拟执行.
Aiming at the requirements specification and related checking of embedded real-time software, a visual modeling language, RTRSM* (real-time requirements specification model*), which is compositional and based on hierarchical and concurrent finite state machine, is proposed. It uses state transitions with duration and scheduled events to describe timing constraints, and can support the description of interactivity and timing constraints effectively. Additionally, RITL (real-time interval temporal logic), a kind of prepositional temporal logic, is presented to make up for RTRSM*抯 defect description of global system properties, which is the drawback of operational specification languages. Interpreted over timed state sequences, RITL is able to deal with the description of both point-based and interval-based metric temporal properties, and supports the property description of RTRSM* models naturally and comprehensively. The verification and validation of the resulted requirements specification, especially issues with respect to the reachability graph of RTRSM* models with finite system states and the simulation execution of the specification, are also explored.
出处
《软件学报》
EI
CSCD
北大核心
2004年第11期1595-1606,共12页
Journal of Software
基金
国家自然科学基金
香港王宽诚教育基金~~
关键词
嵌入式实时软件
需求规约语言
需求规约检测
可达图
embedded real-time software
requirements specification language
requirements specification checking
reachability graph
